Senior Verification Engineer at P Chappel Associates Inc

Senior Verification Engineer to support verification and validation of complex FPGA-based systems for aerospace, defense, and space applications. This role focuses on FPGA verification (VHDL/Verilog), simulation, test strategies, protocols, and certification activities. Position Summary The Senior Verification Engineer will develop verification plans, build testbenches, run simulations, and ensure first-pass success of FPGA designs. You will work closely with design, hardware, and software teams while supporting certification and documentation requirements. Key Responsibilities Develop and execute FPGA verification and validation plans, test strategies, and methodologies. Create simulation environments, testbenches, and run regression testing. Verify designs written in VHDL and support verification using Verilog/SystemVerilog. Debug FPGA issues and collaborate with cross-functional engineering teams. Work with Xilinx Vivado tools and ModelSim/Questa for simulation. Validate high-speed interfaces and protocols including PCIe, 1G/10G Ethernet, and TSN. Support DO-254/178C certification activities and documentation. Mentor junior engineers and contribute to continuous improvement of verification processes. Qualifications Bachelor’s or Master’s in Electrical or Computer Engineering. 8–15 years of FPGA verification experience. Strong expertise in VHDL, with working knowledge of Verilog/SystemVerilog and UVM. Proficiency with Xilinx Vivado; experience with Intel Quartus or Lattice Diamond is a plus. Experience with ModelSim/Questa and Xilinx ILA. Solid understanding of FPGA architecture and digital design. Hands-on experience with PCIe, 1G/10G Ethernet, TSN. Experience supporting DO-254/178C certification processes. Strong debugging, analytical, and communication skills.