ASIC Intern at Etched

ASIC InternLocation: San Jose CA Team: Hardware Engineering (ASIC)About EtchedEtched is building the worlds first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs you can build products that would be impossible with GPUs like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers Etched is redefining the infrastructure layer for the fastest growing industry in history.Job SummaryWe are seeking highly motivated hardware engineering interns to join our team. We are looking for interns across RTL Design Physical Design and Design Verification. You do not need experience across all three tracks. Strength in one area (RTL PD or DV) is sufficient.As an RTL Intern at Etched you will help design and implement the digital logic that powers our ASICs. You will work with cutting-edge machine learning architectures contribute to RTL block development and participate in the full design cyclefrom microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced high-autonomy environment.As a Physical Design intern you will be responsible for working to implement and verify physical designs and will help Etched as we work to improve iteration speed on physical design. You will assist in running Physical Design flows to close blocks support ASIC infrastructure automate Physical Design flows and improve CAD infrastructure.As a Design Verification intern you will ensure the custom IPs powering Sohu including systolic arrays DMA engines and NoCs are robust high-performance and silicon-ready. This role demands creativity deep technical ability and the drive to tackle complex verification challenges. You will collaborate with architects RTL designers and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.You may be a good fit if you have:Progress towards a Bachelors Masters or PhD degree in computer science computer engineering or a related field.Familiarity with high-speed digital logicExposure to ASIC or SoC design conceptsFamiliarity with Verilog or SystemVerilog (RTL/DV)Familiarity with verification work and writing test benches (DV)Interest in physical design flows and tooling (PD)Are able to learn quickly about transformers and other aspects of modern artificial intelligenceStrong candidates may also have experience with:Familiarity with transformer models and machine learningFamiliarity with numerical representations and functions (RTL)Familiarity with clock domain crossing (RTL/PD)UVM or formal verification experience (DV)Ability to program with Python or another scripting languageWe encourage you to apply even if you do not believe you meet every single qualification.Program Details:12-week paid internship (June - August 2026)Generous housing support for those relocatingDaily lunch and dinner in our officeBased at our office in San Jose CADirect mentorship from industry leaders and world-class engineersOpportunity to work on one of the most important problems of our timeFor any questions contact .How were differentEtched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures which creates a market for single-model ASICs.We are a fully in-person team in West San Jose and greatly value engineering skills. We do not have boundaries between engineering and research and we expect all of our technical staff to contribute to both as needed.Required Experience:Intern Key Skills Campaigns,Abinitio,AutoCAD 3D,Hardware & Networking,Customer Support,Arabic Employment Type : Full-Time Experience: years Vacancy: 1