Design Verification Engineer at Programmers.io

Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases perform coverage analysis and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve issues Execute regression runs analyze results and contribute to continuous improvements Integrate and run power-aware simulations low power checks and work with UPF/CPF as needed Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains Document test environments testplans and results for internal and external reviews Key Skills Arabic Speaking,Logistics Operations,Lecturing,Community Support,Gynaecology & Obstetrics,AC Maintenance Employment Type : Full Time Experience: years Vacancy: 1