Mixed-Signal Senior Verification Engineer | Series-D Semiconductor Innovator at Trispoke managed services

Mixed-Signal / Senior Verification Engineer Series-D Semiconductor Innovator Austin TX (Onsite) Our client is a Series-D semiconductor innovator building cutting-edge programmable coherent DSP solutions for cloud and AI infrastructure-technology that powers high-speed energy-efficient data transmission for next-gen AI data centers. Backed by top-tier investors (Kleiner Perkins Spark Capital Mayfield Fidelity) the company recently emerged from stealth with $180M funding and is scaling rapidly. We are hiring Mixed-Signal Verification Engineers and Senior Digital Verification Engineers to work on next-generation high-speed communication technology. Location: Austin TX (Onsite 5 Days/Week Mandatory) Full-time roles H1B Sponsorship Available Meaningful Equity Full Medical/Dental/Vision Compensation: $160000 $200000 Equity (4-year vesting) About the Role You will be part of an elite engineering team developing high-performance DSP and communication silicon for cloud AI and hyperscale infrastructure. These roles focus on mixed-signal verification digital block/system verification and behavioral modeling for highly complex ICs. Key Responsibilities Mixed-Signal Verification Develop verification strategies for mixed-signal (digital analog) designs using UVM. Create behavioural models (BM) for analog blocks per designer guidance. Write execute and debug System Verilog/UVM testbenches for mixed-signal blocks. Run behavioral model validation using AMS tools. Perform unit-level cluster-level and top-level simulations. Digital / Senior Verification Plan & perform verification of complex digital design blocks per specifications. Build verification environments using System Verilog UVM Specman or SystemC. Identify and write coverage measures for all corner cases. Debug functionality with design teams; drive full functional coverage closure. Execute 2 full block or system-level verification cycles. Must-Have Qualifications Minimum 5 years Behavioral Modeling (BM) of analog design for digital verification 7 10 years experience in digital/mixed-signal verification Experience in Verilog / SystemVerilog coding Strong knowledge of VLSI verification flows & concepts Hands-on with UVM eRM OVM Specman or SystemC Experience with digital design tools (no AMS required) Strong understanding of functional block/cluster testing Must have completed 2 full block/system verification cycles Job stability - No job hoppers; no employment gaps Onsite availability (Austin TX 5 days/week) Preferred Qualifications Experience with Virtuoso Schematics Experience with Synopsys and Cadence tools Experience with data path / data protocol verification (Ethernet preferred) Ability to develop scalable reusable test cases Strong written and verbal communication; able to write test plans & present results Collaborative mindset for working in cross-functional engineering teams Compensation & Benefits Salary: $160000 $200000 Meaningful Equity (4-year vesting) H1B Sponsorship available Full Medical Dental Vision benefits Relocation support (case-by-case) 3-round interview process (2 weeks) #VerificationEngineer #MixedSignalVerification #DigitalVerification #SystemVerilog #UVM #VLSIJobs #SemiconductorJobs #DSP #ChipDesign #ASICVerification #HardwareEngineering #EDA #AustinJobs #HiringNow #TechCareers #EngineeringJobs #AIInfrastructure #HighSpeedCommunication #AnalogDesign #SiliconEngineering Key Skills Apache Web Server,C++,Community Support,Bakery,Islamic Banking Employment Type : Full Time Experience: years Vacancy: 1