Senior Principal Emulation Design Engineer at Cadence Systems

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.We are seeking a highly skilledDesign Engineer to join our Palladium Solutions Development team to drive the development of full-system design verification environments. This role focuses ondeveloping and integrating and validating high speed interface Serdes Chip 2 chip link based subsystems in Emulation Platforms. Development includes Parallel and Serial models for highspeed interface circuits in analog Mixed Signal Designs and components(PHYs). Integration includes thePHY Controller / Mac andthe Accelerable Verification IP (AVIP)environments on Palladiumand Protium. End-to-end verificationflowdevelopmentacross a wide range of system componentsincluding custom test case developments validating the bare-metal-driver components in emulation platforms.Key Responsibilities:Lead the design and deployment of PHY logic modelsfor emulation platforms including Palladiumand Protium.Develop and maintain end-to-end verification environments encompassing:System-level modelsincluding microcontrollers memories NoC (Network-on-Chip) and high-speed communication interfacesTest case generationInterface Circuit Performance Analysis.Contribute to system prototypingfor early bring-up and validation of full-system designs.Collaborate with cross-functional teams to ensure seamless integration from simulation to emulation.Optimize designs for multi-clock domain synchronization area and performance with a focus on accuracy vs. runtime trade-offs.Drive innovation inemulatableIP solutions and contribute to the evolution of verification methodologies.Required Qualifications:Bachelors or Masters degree in Electrical Engineering Computer Engineering or related field with 7-15 years of experienceStrong experience with system-level design and communication standards such as PCIe UCIe EthernetUALinkDDR USB SPI JTAG AMBA protocolsProficiency in:Converting Analog Mixed Signal DesignsParallel and Serial modelsto emulation models maintainingfunctional and bitaccuracy enabling software stack development for configuration control and status monitoring.SystemVerilogfor synthesizable RTL designC and Pythonfor modeling scripting and automationLab debug and test case developmentHands-on experience with emulation platforms:Palladium Protium ZebuHAPSVelociFPGADeep understanding of verification flows and emulation acceleration techniques.Preferred Skills:Experience building emulatableAVIP solutionsFamiliarity with end-to-end verification environmentsfrom simulation through emulationExperience in system prototyping and bring-upStrong analytical and problem-solving skillsExcellent communication and leadership abilitiesWere doing work that matters. Help us solve what others cant.The annual salary range for California is $154000 to $286000. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.Were doing work that matters. Help us solve what others cant.Required Experience:Staff IC Key Skills GP,Maintenance Planning,ASP.NET,Food Processing,Catia Employment Type : Full-Time Experience: years Vacancy: 1 Monthly Salary Salary: 154000 - 286000