Senior Technical Staff Engineer Architect (DFT Lead) at Microchip

Are you looking for a unique opportunity to be a part of something great Want to join a 17000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust empowerment respect diversity and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development values-based decision making and strong sense of community driven by our Vision Mission and 11 Guiding Values; we affectionately refer to it as the Aggregate System and its won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.Visit our careers page to see what exciting opportunities and company perks await!Job Description:Microchip Technology Inc. has a Senior Technical Staff Engineer - Architect (DFT Lead) opening based in Austin TX.The DFT lead works in close partnership with different teams within the FPGA business unit spanning architecture ASIC design verification physical implementation and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from the initial investigation and feasibility to tape-out as well as silicon validation and characterization of test methods on Automatic Test Equipment (ATE).ResponsibilitiesManage DFT requirements across architecture design and product teams to ensure coverage die cost test cost and DFT integration requirements are met at the block and full chip level. Define implement and validate DFT features at the FPGA full chip and sub-systems levelCollaborate closely with cross functional teams to support DFT insertion synthesis scan insertion place-and-route static timing analysis timing closure power analysis during test and quantifying full chip test coverageEstablish and maintain DFT design and insertion guidelines and documents best practices for all development teams to followBe current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and qualityWork with Test and Product engineers to support development of firmware targeted test patterns ATPG and mBIST test feature validation processes and silicon debug activitiesCommunicate project status and progress to chip lead and engineering managementRequirements/Qualifications:Bachelors or Masters in engineering field15 years of DFT engineering experience through DFT pre and post silicon cyclesExperience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodesExpert level knowledge about IJTAG and JTAG test access Streaming Scan Network (SSN) scan compression and insertion SAF/TDF/PDF ATPG memory BIST and repair logic BIST MISRs at-speed testing of SoC/FPGA fault simulation quantifying full chip test coverage DFT mode timing constraints and power control during testFamiliar with DFT verification silicon debug memory and scan diagnosticsExperience in PHY high-speed IO digital communication and functional test developmentGood understanding of Verilog synthesis physical implementation and STAGood understanding of verification methodologyPreferred Skills and Experience:Knowledge of FPGA design flowKnowledge of embedded design and firmware methodologyUnderstanding Arm or RISC IPs high speed interfaces such as PAM4 SerDes DDR4/5 etc.Experience in leading multiple FPGA/SoC projects.Travel Time:0% - 25%Physical Attributes:Feeling Hearing Other Seeing Supervises Others Talking Works Alone Works Around OthersPhysical Requirements:15% walking 15% standing 70% sitting 100% in doors; Usual business hoursMicrochip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex gender identity sexual orientation race color religion national origin disability protected Veteran status age or any other characteristic protected by law.For more information on applicable equal employment regulations please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.Required Experience:Staff IC Key Skills APIs,SOAP,Software Architecture,.NET,Design Patterns,Enterprise Software,AWS,Solution Architecture,Cloud Architecture,Java,SSO,Oracle Employment Type : Full-Time Experience: years Vacancy: 1