Sr Principal Design Engineer at Cadence Systems

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.Specific duties include:Be responsible for high-performance memory IP architecture design owning the IC micro-architecture timing budget power analysis platform development.Proficiency in logic design simulation synthesis STA and testingProficiency in Verilog/SystemVerilog and its simulation environmentGood knowledge of IC design for high-speed and low powerAt least five years experience driving complex IC development projects excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.Position Requirements: Essential Qualifications: Must have BS degree with 8 years of applicable experience MS degree with 6 years of applicable experience in electrical engineering microelectronics comparable engineering science or solid state physics.Essential that the individual demonstrates strong communication verbal and written.Experience on the memory IP is desiredRequires good communication skills in English.The annual salary range for California is $154000 to $286000. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.Were doing work that matters. Help us solve what others cant.Required Experience:Staff IC Key Skills Design,Academics,AutoCAD 3D,Cafe,Fabrication,Java Employment Type : Full-Time Experience: years Vacancy: 1 Monthly Salary Salary: 154000 - 286000